The present disclosure relates to a semiconductor integrated circuit in which a protected circuit and a protective circuit that removes a surge generated in a power supply line of the protected circuit are formed in a same semiconductor substrate.
In general, for the semiconductor integrated circuit such as a large scale integrated circuit (LSI), the importance of protecting a circuit having a predetermined function (hereinafter, referred to as internal circuit or protected circuit) from a surge generated in a power supply line of the internal circuit is increasing along with miniaturization and voltage decrease of the semiconductor integrated circuit.
As a representative example of the surge generated in the power supply line, an ESD surge, which suddenly raises the power supply line voltage due to an electrostatic discharge (ESD) to an external terminal of the power supply line, is known.
For the purpose of preventing the internal circuit from being broken down when a high voltage pulse is generated at the external terminal due to the ESD surge, an element or a circuit for ESD protection is integrated in the semiconductor substrate together with the internal circuit (protected circuit).
As the element or the circuit for ESD protection, a gate grounded metal oxide semiconductor (GGMOS), a thyristor, a resister-capacitor MOS (RCMOS), and so forth are known. The respective elements and circuits for ESD protection are accordingly used depending on the use purpose. In recent years, the protective circuit having the RCMOS configuration, which can be designed comparatively easily, is frequently used.
FIG. 1 is a circuit configuration diagram of an ESD protective circuit having the RCMOS configuration. FIG. 1 is a diagram based on a technique disclosed in a non-patent document, C. A. Torres et al; “Modular, Portable, and Easily Simulated ESD Protection Networks for Advanced CMOS Technologies,” Electrical Overstress/Electrostatic Discharge Symposium, September 11-13. Symposium Proceedings, P. 81-94, FIG. 1. The circuit configuration and the operations thereof will be described below.
Many internal circuits have a complementary MOS (CMOS) configuration, and an ESD protective circuit 1 having the RCMOS configuration shown in FIG. 1 uses a detecting element including a resistor (R) and a capacitor (C) and a CMOS circuit such as an inverter as a configuration having high process affinity with an internal circuit 6. This ESD protective circuit 1 has a resistive element R, a capacitive element C, a CMOS inverter circuit 4, and a protection transistor 5 connected between a power supply line 2 and a reference voltage line 3 as shown in the diagram.
Specifically, in the ESD protective circuit 1, a MOS transistor (hereinafter, protection transistor) 5 that discharges a high voltage pulse generated in the power supply line 2 attributed to an ESD to the reference voltage line 3 is disposed between the power supply line 2 and the reference voltage line 3. A drain and a source of the protection transistor 5 are connected to the power supply line 2 and the reference voltage line 3, respectively. Furthermore, the resistive element R and the capacitive element C are connected in series between the power supply line 2 and the reference voltage line 3 to configure an RC series circuit. In addition, an inter-element node is connected to an input of the CMOS inverter circuit 4 and an output of the CMOS inverter circuit 4 is connected to a gate of the protection transistor 5.
This ESD protective circuit 1 is so designed as not to react to normal potential rise, fluctuation, and so forth of a power supply line by utilizing a time constant based on the resistive element R and the capacitive element C.
In the case of intentionally raising the potential of the power supply line 2 like the case of normal power activation, the rising speed of the pulse is lower than that at the time of ESD surge generation. Therefore, a potential VRC of the node connecting the resistive element R and the capacitive element C rises up without a long delay from the rise of the potential of the power supply line 2.
In contrast, if a pulse with a frequency higher than that assumed in normal operation (e.g. ESD surge) is applied to the power supply line 2, the potential VRC of the node connecting the resistive element R and the capacitive element C in the RC series circuit rises up with a delay from the potential rise of the power supply line 2. The potential rise in a human body model (HBM), which is a representative model of the ESD, occurs in an extremely-short time of several hundreds of nanoseconds, and the time constant of the RC series circuit is so determined that the above-described potential VRC rises up with a delay from the potential rise of the power supply line 2 responding to the potential rise with such a high frequency.
If the potential VRC rises up with a delay from the rise of the potential of the power supply line 2, a positive pulse generated in the CMOS inverter circuit 4 is applied to the gate of the protection transistor 5 for only the period until the potential VRC reaches the threshold value of the inverter of the CMOS inverter circuit 4.
Thus, the protection transistor 5 is in an on-state for only the time defined by this positive pulse to remove the ESD surge from the power supply line 2 to the reference voltage line 3. Therefore, the internal circuit 6 connected between the power supply line 2 and the reference voltage line 3 is protected from the ESD surge.
When the potential VRC reaches the threshold value of the inverter of the CMOS inverter circuit 4, the positive pulse applied to the gate of the protection transistor 5 ends, and thus this transistor is immediately turned off.
In this manner, the ESD protective circuit having the RCMOS configuration detects the ESD surge by the detecting circuit (RC series circuit) using the resistor (R) and the capacitor (C) and immediately removes the ESD surge from the power supply line in response to the detection result by this detecting circuit.